1. Field
This patent document relates to a latch circuit and a latch circuit array including the same.
2. Description of the Related Art
A latch circuit for storing data is one of the most frequently used circuits amongst all types of semiconductor devices. With the increase in integration degree of semiconductor devices, the capacitance of storage nodes in the latch circuits has decreased, leading to an increase in soft errors. Soft errors are the corruption of data in storage nodes of a latch circuit, commonly cause by cosmic rays, by way of alpha particles.
A variety of latch circuits with resistance to soft errors have been proposed. One of the proposed latch circuits is the dual interlocked storage cell (DICE), which has been disclosed in Calin et al., “Upset Hardened Memory Design for Submicron CMOS Technology”, IEEE Transactions on Nuclear Science, vol 43, No. 6 Dec. 1996.
FIG. 1 is a circuit diagram illustrating the DICE.
Referring to FIG. 1, the latch circuit includes first to fourth storage nodes SN1 to SN4, first to fourth pairs of transistors 110 to 140, and an input unit 150.
The pairs of transistors 110 to 140 include PMOS transistors 111 to 141 and NMOS transistors 112 to 142, respectively, which are coupled in series at corresponding storage nodes SN1 to SN4. Gates of the NMOS transistor of the previous one of the first to fourth pairs of transistors 110 to 140 and the PMOS transistor of the next one of the first to fourth pairs of transistors 110 to 140 may be coupled at one of the storage nodes SN1 to SN4 included in the current one of the first to fourth pairs of transistors 110 to 140. For example, the gates of the NMOS transistor 112 of the first pair of transistors 110 and the PMOS transistor 131 of the third pair of transistors 130 may be coupled at the second storage node SN2 of the second pair of transistors 120. The next one of the last pair of transistors 140 may be the first pair of transistors 110. Similarly, the previous one of the first pair of transistors 110 may be the last pair of transistors 140.
The input unit 150 includes four NMOS transistors 151 to 154. The input unit 150 is turned on when a clock CK is activated, and transmits data of a data line D to the storage nodes SN1 and SN3, or transmits data of an inverted data line DB to the storage nodes SN2 and SN4. The storage nodes SN1 and SN3 have a reverse polarity to the storage nodes SN2 and SN4.
The latch circuit of FIG. 1 has strong immunity to soft errors caused by cosmic rays. Only when the data of two or more storage nodes SN1 to SN4 simultaneously changes due to cosmic rays will the data stored in the latch circuit be corrupted by soft errors. For example, although the data of the first storage node SN1 changes from a logic high (“H”) to a logic low (“L”) due to the cosmic rays when the data set ‘H, L, H, L’ is respectively stored in the storage nodes SN1 to SN4, the data of the first storage node SN1 may change from “L” to “H” due to the PMOS transistor 111. In other words, soft errors do not occur unless the data of two or more storage nodes simultaneously changes due to cosmic rays in the latch circuit. The probability of simultaneous data change of two or more storage nodes due to the cosmic rays is extremely low.
The latch circuit of FIG. 1 has the advantage of being resistant to errors caused by cosmic rays. However, since the data of the latch circuit are not easily changed, an error may easily occur while data are inputted to the latch circuit.